On October 9th， according to a report from Kuaitech， just six months after the unveiling of the “PoX” picosecond flash memory device， Fudan University has achieved another milestone in the engineering of two-dimensional electronic devices.
Fudan University has announced that the “CY-01” architecture， developed by the Zhou Peng-Liu Chunsen team at the university， integrates the two-dimensional ultrafast flash memory device “PoX” with mature silicon-based CMOS technology. This integration has led to the development of the world’s first mixed two-dimensional-silicon hybrid architecture chip.
The research findings were published on the evening of October 8th， Beijing time， in the journal Nature， under the title “A full-featured 2D flash chip enabled by system integration.”
Fudan University states that this breakthrough overcomes critical challenges in the engineering of novel two-dimensional information devices. It provides a paradigm for shortening the application cycle of next-generation disruptive devices and offers strong support for ushering in a new era of high-speed information technology.
The packaged two-dimensional-silicon hybrid architecture flash memory chip (with PCB board)
Currently， CMOS technology is the mainstream process for integrated circuit manufacturing. Most integrated circuit chips on the market are manufactured using CMOS technology， with a relatively mature industrial chain.
The research team believes that to accelerate the incubation of new technologies， it is essential to fully integrate two-dimensional ultrafast flash memory devices into the traditional semiconductor production lines of CMOS. This integration can also bring about new breakthroughs for CMOS technology itself.
The chip， based on CMOS circuitry controlling the two-dimensional storage core， supports 8-bit instruction operations， 32-bit high-speed parallel operations， and random addressing， achieving a yield rate as high as 94.3%. This marks the world’s first two-dimensional-silicon hybrid architecture flash memory chip， significantly outperforming current Flash memory technology and representing the first successful engineering of a hybrid architecture.
It is understood that the surface of CMOS circuits is characterized by numerous components， akin to a miniature “city” with varying elevations. In contrast， two-dimensional semiconductor materials are only 1-3 atoms thick， as delicate and fragile as a “cicada’s wing.” Directly layering these materials onto CMOS circuits would likely cause them to crack， rendering circuit performance unattainable.
The core challenge for the team was to integrate these two-dimensional materials with CMOS without compromising their performance.
The team opted to start with two-dimensional materials that possess inherent flexibility. Through a modular integration approach， they first manufactured the two-dimensional storage circuits and mature CMOS circuits separately. Then， using high-density monolithic interconnection technology (micrometer-scale vias)， they achieved complete chip integration with the CMOS control circuitry.
A structural schematic of the two-dimensional-silicon hybrid architecture flash memory chip， showing the 2D module， CMOS control circuitry， and micrometer-scale vias.
This innovative core manufacturing process enables close adhesion between the two-dimensional materials and the CMOS substrate at the atomic scale， ultimately achieving a chip yield rate exceeding 94%.
Leveraging the research and integration work completed previously， the chip has now been successfully fabricated.
In the next phase， the team plans to establish an experimental base and collaborate with relevant institutions to initiate an independently led engineering project. They aim to scale the project to the exabyte level within 3-5 years， with the intellectual property and IPs generated during this period available for licensing to partner companies.
An optical micrograph of the two-dimensional-silicon hybrid architecture flash memory chip
